In electronic instrumentation systems, it is frequently necessary to accept an analogue value (i.e. a continuously varying electrical signal) and to transform the value of that signal into a digital representation for subsequent processing.
Such a digital representation is commonly made as a binary fraction of some known "reference" value, that is the "quantity" is represented as a N-bit binary number, whose value X denotes the Quantity thus
Quantity=Reference x(X/2.sup.N),
where the value X may range from zero to 2.sup.N -1.
This notation may represent real quantities from zero to just less than the chosen Reference value. For example, if the Reference value is chosen as 10.24V (i.e. 2.sup.10 .times.0.01V), and the digital representation is in 10 bits, we may represent voltages from zero to 10.23V, to within an accuracy of 0.01V.
Many techniques for executing Analogue-to-Digital conversion have been described in such standard texts as "Bipolar and MOS Analog Integrated Circuit Design" (Grebene A., John Wiley, 1984). The present invention is of specific application to converters employing the so-called "Successive Approximation" method, which is known.
A technique of logic design practiced in Very Large-Scale Integration (VLSI) circuits, is the so-called "dynamic" technique (see, inter alia, Mead and Conway, "Introduction to VLSI Systems", Addision-Wesley, 1980). This scheme relies upon the short-term storage of information as electrical charges in stray wiring capacitance. Adroitly used, this method can result in considerable reductions in circuit complexity and power consumption. Its disadvantage is that the electrical charges will slowly "leak" (due to imperfect insulation), resulting in loss of the stored information. It is therefore a characteristic of Dynamic circuits to refresh, that is any information so stored must be periodically read out and re-written to maintain the charge.
According to a known Successive Approximation method of conversion, there is provided at least a Successive-Approximation Register (SAR), a Digital-to-Analogue Converter (DAC), a Comparator, and some form of sequencing or control logic, or as is shown in FIG. 1.
The DAC is adapted to develop an analogue output, equal to the Reference voltage multiplied by the binary fraction stored in the SAR, as described above. Many methods of achieving this are known, for example the so-called "R/2R Ladder" method as illustrated in FIG. 2. As may be seen, the circuit comprises an array of switches adapted to switch between Ground and the Reference voltage, and an array of resistances, being alternately of some value (R) and twice that value (2R). By suitably setting the several switches, voltages between zero (Ground) and Reference may be developed at the output. In a practical ADC, the several switches are adapted to be controlled by the several bits of the SAR.
This output voltage is applied to the Comparator, which develops a logical (i.e. True/False) output indicating whether the DAC output is higher or lower than the unknown analogue input. This logical output is used by the Control Logic to adjust the binary number held in the SAR, so as to bring the DAC output as close as possible to the unknown analogue input.
The operating principle is typically as follows:
The Control Logic begins by setting all the SAR bits to Zero. The most significant SAR bit is then preset to One, and the Comparator output is tested. If the DAC output is found to be higher than the unknown input, the SAR bit is cleared or reset back to Zero, otherwise it remains set to One. The Control Logic then presets the next lower significance SAR bit, and proceeds similarly, until all SAR bits have been processed.
Conveniently, a given SAR bit is preset to One, simultaneously with the selective resetting of its predecessor.
When this process is complete, the required digital representation of the unknown input is held in the SAR bits. The requirement to maintain the SAR output for extended periods of time usually precludes the use of Dynamic logic (as aforedescribed) in practical SAR designs.
This technique is widely used in practical devices.
It will be apparent that at least two Data Storage Means are required namely, the SAR bits themselves, and some further means (assumed in the above example to be contained within the control logic) to keep track of which SAR bit is currently being processed.
Practical systems have utilised either a counter or a shift register circuit to perform this latter (bit addressing) function. An example of the shift-register technique may be found in the 74LS502 SAR integrated circuit (Fairchild Semiconductor, Inc.) whose operation is described in the manufacturer's data sheets.
It will be appreciated that when two shift registers are used, the second (addressing) register consumes a similar amount of electronic circuitry (area) to the actual SAR register itself. Counter-based systems consume a similar amount of extra circuitry for the requisite Counter and Decoder. Heretofore, it has not proved possible to eliminate this extra circuitry. Clearly such elimination would be desirable, leading to greater economy in manufacture than has heretofore been possible.
There are numerous prior art pertaining to SAR design and to Analogue-to-Digital conversion and particularly orientating toward improving the speed of operation of the SAR rather than seeking to reduce the circuit complexity. Some known prior art are U.S. Pat. No. 4,527,148, U.S. Pat. No. 4,764,750, EP258840, EP 258841.
Others, for example U.S. Pat. No. 4,654,584, relate to various forms of Analogue-to-Digital Converters rather than to the internal functioning of SAR.
In U.S. Pat. No. 4,688,018, the problem of SAR design is addressed. However, it discloses and requires separate Shift Register (SHR1, SHR2, SHR3, SHR4) and SAR storage cells (12, 14) rather than a single storage cell to perform both functions of bit addressing and accumulating the result. Further, the use of separate Shift Register and SAR latches necessitates additional serial signal paths (8 in U.S. Pat. No. 4,688,018) between successive stages.
Furthermore, the operation of the SAR latch (36) requires that the string of set/reset transistors (52, 54, 56) have a greater electrical conductivity than the latch transistors (inverter 38). This arrangement of differentially conductive transistors may preclude fabrication of circuits according to a form of semiconductor chip design on so called "Gate Array" devices, characterized by a multitude of transistors all of a standard size, thus able to offer low design and set-up costs. To modify such circuit arrangement to eliminate the requirement for differentially conductive transistors, significantly more transistors may be required for the modified design.
U.S. Pat. No. 4,441,198 is intended to increase the operating speed of SAR using both edges of the clock signal. Two latch elements per bit of the SAR are disclosed.